This non-provisional application claims priority under 35 U.S.C. § 119(a) on Korean Patent Application No. 2005-5444 filed on Jan. 20, 2005, which is herein expressly incorporated by reference.
1. Field of the Invention
Embodiments of the present invention relate to a method of driving a memory device to implement multiple states. More particularly, embodiments of the present invention relate to a method of driving a memory device which includes an organic memory layer interposed between upper and lower electrodes so as to implement multiple states, in which switching using multiple pulses and typical switching using negative differential resistance (NDR) are employed to fabricate multi-state memory having at least three different resistance states.
2. Description of the Related Art
In accordance with recent advances in the information communication industry, demand for various memory devices is rapidly growing. Particularly, it is required that memory devices for mobile terminals, various kinds of smart cards, electronic money, digital cameras, memories for game, or MP3 players have nonvolatility so as to prevent recorded information from being erased even when power is turned off. Of nonvolatile memories, recently, flash memory based on silicon material has monopolized the market.
In conventional flash memory, the number of record/erase operations is limited, recording speed is slow, and a microfabrication process must be conducted to reduce the width of wire per unit area so as to create highly integrated memory capacity. With respect to this, there is a limit in that the fabrication cost of a memory chip increases as the cost of the above process increases and it is difficult to miniaturize the chip due to this technical limit. In accordance with disclosure of the technical limit of the conventional flash memory as described above, much effort has been made to develop a next generation nonvolatile memory device having ultrahigh speed, high capacity, low power consumption, and low price characteristics so as to avoid the physical limits of conventional silicon memory devices.
Next generation memory is classified into ferroelectric RAM, magnetic RAM, phase change RAM, nanotube memory, holographic memory, and organic memory depending on the material constituting a cell as a basic unit of a semiconductor. Of them, in organic memory, organic material is interposed between upper and lower electrodes, and voltage is applied thereto to impart memory characteristics using bistability of a resistance value. In other words, organic memory is memory in which the resistance of the organic material between the upper and lower electrodes is reversibly changed by electric signals to record and read data ‘0’ and ‘1’. Organic memory is largely expected to be the next generation memory because it implements nonvolatility, which is the advantage of conventional flash memory, and because it can avoid problems pertaining to processability, fabrication cost, and integration.
Japanese Patent Laid-Open Publication No. Sho. 62-95882 discloses a memory device using CuTCNQ (7,7,8,8-tetracyano-p-quinodimethane), that is, an organometallic complex charge transfer compound. U.S. Patent No. 2002-163057 introduces a semiconductor device comprising an intermediate layer in which ionic salts, such as NaCl or CsCl, are mixed with conductive polymer and which is interposed between upper and lower electrodes.
U.S. Patent No. 2004-27849 suggests an organic memory device in which metal nanoclusters are interposed between organic memory layers. However, this device is problematic in that it is very difficult to form the metal nanoclusters because of very low yield, and it is practically impossible to use it as a nonvolatile memory because of a rest phenomenon at OV voltage.
Meanwhile, a large-capacity memory device is required according to development in the informatization industry, and, recently, many studies have been conducted of a multi-bit, multi-level, or multi-state memory device as a technology for storing data having a plurality of bits in one memory cell so as to improve integration of the memory device. It is of essential importance in a large-capacity storage device to reduce the cost per bit. In order to meet this requirement, a technology significantly reducing the cost per bit of a flash EEPROM device is disclosed in IEEE, ISSCC Digest of Technical Papers, pp. 132-133, M. Bauer et al., February 1995, which is entitled “A Multilevel-Cell 32 Mb Flash Memory”. The flash memory device disclosed in the above-mentioned document has a reduced cell size and 4 levels for 2 bits. In the flash memory device, if data corresponding to 4 levels for 2 bits are expressed using binary numbers, they correspond to 00, 01, 10, and 11, and predetermined threshold voltage levels are set corresponding to data, for example, 0=2.5 V, 1=1.5 V, 10=0.5 V, and 11=−3 V. Each memory cell has any one threshold voltage level of the four threshold voltage levels, and a binary datum of the binary data, such as 00, 01, 10, and 11, corresponding to the predetermined threshold voltage, is stored in the memory cell. As described above, typically, the multi-state flash memory device has two or more threshold voltage distributions and states corresponding to the threshold voltages (Vth).
U.S. Pat. No. 5,270,965 discloses a method of driving a memory device having a MIM (metal-insulator-metal) structure, which is capable of being operated in multiple values without a complicated fabrication process. In detail, it discloses the method of driving the memory device in which an organic memory layer is sandwiched between a pair of electrodes. The method comprises applying a first voltage higher than a predetermined voltage range between a pair of electrodes of the memory device to switch the device, in a first resistance state corresponding to a first resistance value of at least three resistance values, so as to be in a second resistance state of at least three resistance states; and applying a second voltage higher than a predetermined voltage range between a pair of electrodes of the memory device to switch the device, in the second resistance state corresponding to a second resistance value of at least three resistance values, so as to be in a third resistance state of at least three resistance states. However, this method is problematic in that, since reproducibility is low, practical usability is doubtful, and transition and switching among the states can be achieved only in a circulation manner.